1. Field of the Invention
This invention relates to a current cell playing a role as a current switch source in a digital-to-analog converter.
2. Description of the Prior Art
The structure of digital-to-analog converter (hereinafter `D/A converter`) to convert digital signal to analog signal is assembled in two parts, wherein one part is to generate the output current equivalent to digital value by separating the digital signal as a constant signal group and the other part is to generate the optimal output current corresponding to the said digital value.
The major performance characteristics of the D/A converter in accordance with the current switch cell and its type are as follows:
A) Linearity: This depends on the symmetrical operation of the current switching cell, and is affected by the output impedance of current source. Hence, as the matching between current sources affects the symmetrical switching operation, the current cell in differential type is suitable in terms of linearity.
B) Glitch: This depends on the incomplete synchronization of digital input signal determining on-and off-state of the current source. The glitch is related to the decoding circuit generating the digital input signal which reaches each current source, thus creating the current switch cell of differential type in the state of non-symmetrical switching. Accordingly, the performance of inverter consisting of the differential type should be considered.
C) Operation speed: The operation speed of the current switch cell is affected by the stray capacitance in output node. To reduce the said effect, common source stray capacitance should be minimized to make the switching-recovery time smaller.
FIG. 1 illustrates a circuit diagram of the current cell playing a role of current switch source, which is a basic structure of conventional D/A converter.
The current cell of the prior art comprises 3 pieces of p-type MOS transistor M1-M3. Voltage Vcmp is applied to the gate terminal of p-type MOS transistor M1, and the power supply voltage Vdd is applied to its source terminal. The drain terminal of the transistor M1 is connected to the source terminal of p-type MOS transistors M2, M3 and the drain terminals of MOS transistor M2, M3, where the digital input signal Di and reference voltage Vref are applied to their gate terminal respectively, is connected to ground (GND) and input terminal respectively.
The operation profile of the current cell in the prior art is that the output current (Iout) of the current cell is determined by reference voltage (Vcmp) supplied to the gate of MOS transistor M1, and the signal digital input Di, determining on or off-state of output of the current cell, is supplied to the gate of MOS transistor M2. MOS transistor M3, to which a constant reference voltage Vref is applied, is connected with the said MOS transistor M2 to assist the output switching.
If the said current cell as aforementioned employs various kinds of current switch cell simultaneously, however, the matching of on or off-state in each of current switch cell cannot be made available which may in turn affect the performance characteristics e.g., linearity.
FIG. 2 illustrates a circuit diagram of the current cell for another prior art D/A converter.
The current cell in FIG. 2 comprises 3 p-type MOS transistors M1-M3 and one inverter IN1 in the same manner as in FIG. 1. Reference voltage Vref is applied to the gate terminal of MOS transistor (M1), where the power supply voltage Vdd is applied to its source terminal and the drain terminal is connected to the source terminal of MOS transistors M2, M3. The drain terminal of MOS transistor M2, M3, where both digital input signal Di and inverted digital input signal Di are applied to gate terminal respectively, is assembled to generate both inverted output signal Iout and output signal Iout.
The operation profile of the current cell in the prior art is that instead of applying a constant reference voltage Vref to the gate terminal of MOS transistor M3 which generates the output signal (Iout) as shown in FIG. 1, the digital input signal Di applied to the gate of MOS transistor M2 is inverted and applied to MOS transistor M3. Thus, the switching operation of MOS transistors M2, M3 is in a symmetrical position, which is called `differential type`. In such a D/A converter having the said differential structure, the symmetrical operation of MOS transistor (M2, M3) is of paramount importance.
The current cell as illustrated in FIG. 2 employs the inverter IN1 so as to invert the digital input signal Di applied to the gate terminal of MOS transistor M3. In order for the MOS transistors M2, M3 to be operated in complete symmetry, the difference in delay should not exist between the input time and the output time of data in inverter IN1. However, there has been much difficulty controlling the said difference in inverter.